San Jose, US-United States
Posted 2 weeks ago
| About The Company A leading innovator in lidar technology, this company specializes in designing advanced sensors that enable precise 3D mapping of environments. Their solutions are trusted across various industries, including automotive, smart cities, and industrial automation. By delivering high-performance, cost-effective, and compact lidar systems, they empower the next generation of autonomous driving, robotics, and infrastructure projects. Job Description – Provide technical leadership by creating ASIC verification flow with UVM methodology – Work with design engineers to create both module level and top level comprehensive verification plan for analog and digital IP blocks, as well as SOC system level – Responsible for creating testbench for RTL and gate level simulation with UVM verification methodology – Facilitate coverage benchmark and define design sign-off criteria – Collaborate with FW engineer to bring up SOC verification environment – Assist in FPGA emulation and troubleshooting with simulation testbench Requirement – B.S. or M.S. in Electronic/Electrical Engineering – Minimum 3 years of ASIC UVM verification experience – Hands-on experience in scripting languages (Perl/Tcl/Python/C) and industrial standard verification tools – Proficient in Verilog, System Verilog. – Comprehensive knowledge of ASIC design and verification flow – In depth knowledge of high-speed digital design, multi-clock domain SOC and verification – Coverage driven constraints to verification closure – Experience with netlist simulation. – Good communication skills and a team player – Excellent analytic and problem-solving ability – Self-motivated and able to provide technical leadership |
Job Features
| Job Category | Embedded Systems |
| Seniority | Senior IC / Tech Lead |
| Base Salary | $150,000 - $180,000 |
| Recruiter | nicole.wong@ocbridge.ai |
